E-Book Content
Contents | Zoom in | Zoom out For navigation instructions please click here Search Issue | Next Page __________________ Contents | Zoom in | Zoom out For navigation instructions please click here Search Issue | Next Page Previous Page | Contents | Zoom in | Zoom out | Front Cover | Search Issue | Next Page A BEMaGS F _______________ _____________________________ Previous Page | Contents | Zoom in | Zoom out | Front Cover | Search Issue | Next Page A BEMaGS F Previous Page | Contents | Zoom in | Zoom out | Front Cover | Search Issue | Next Page A BEMaGS F Call for Papers Special Issue on Design and Test of Interconnects for Multicore Chips Guest Editors: Yatin Hoskote (Intel) Radu Marculescu (Carnegie Mellon University) Li-Shiuan Peh (Princeton University) Multicore chips are becoming common in industry, owing to increasing power consumption levels and raw-performance needs. This new paradigm places multiple cores on the same die and connects them through an on-die interconnect, effectively building a network on a chip. The NoC may interconnect identical or heterogeneous cores, depending on the application domain. Choosing the right design is extremely important because the interconnect can consume substantial power and occupy significant real estate in silicon. Although multiple cores have started to appear in real designs, more sophisticated interconnects have only begun to surface with the advent of multicore chips. Design and test methodologies for NoC design constitute a growing concern for future multicore and many-core chip designs. As Moore’s Law enables trillion-transistor chips, and time-to-market pressures push designers to accelerate the design cycle, there is a critical need for CAD tools to help designers achieve NoCs’ tight