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SILICON PROCESSING FOR THE VLSI ERA Vol. 4 – Deep-Submicron Process Technology DETAILED TABLE OF CONTENTS PREFACE
Chap. 1 - THE EVOLUTION OF THE STRUCTURE OF MOSFETS 1.1 THE STRUCTURE OF DEEP-SUBMICRON MOSFETS: (0.25-µm to 0.13-µm) - COMPARED TO THE STRUCTURE OF “CONVENTIONAL” MOSFETS (2.0-µm to 0.5-µm) 2 1.1.1 Evolution of the MOSFET Gate Stack and Contact Structure 1.1.2 Gate Dielectric Materials in Deep-Submicron MOSFETs 1.1.3 Doping-Concentration Profiles of the MOSFET Channel 1.1.4 Evolution of the Drain Structure of MOSFETs 1.2 DEEP-SUBMICRON CMOS STRUCTURES 10 1.2.1 Substrate Issues for Deep-Submicron CMOS 1.2.2 Well Formation in Deep-Submicron CMOS 1.2.3 Dual-Doped Poly in Deep-Submicron CMOS 1.2.4 Shallow Trench Isolation for Deep-Submicron CMOS 1.2.5 Silicon-On-Insulator (SOI) Technology 1.3 LIMITS TO CONVENTIONAL MOSFET SCALING 15 REFERENCES
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Chap. 2 - 300-MM SILICON WAFERS
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2.1 300-mm SILICON CRYSTAL GROWTH 17 2.2 GROWN-IN SILICON DEFECTS: 21 CRYSTAL-ORIGINATED-PARTICLES (COPS) & DISLOCATION LOOPS 2.3 DETAILS OF THE FORMATION OF CRYSTAL-ORIGINATED-PARTICLES (COPS) 23 2.3.1 The Radial Distribution of Grown-In Defects on the Wafer Surface 2.4 THE OXYGEN-STACKING-FAULT RING (OSF-RING) 26 2.5 MITIGATING EFFECTS OF COPS BY USE OF POST-CRYSTAL-GROWTH ANNEALING 27 © 2002 LATTICE PRESS Sunset Beach CA All Rights Reserved
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2.6 ELIMINATION OF COPS WITH “PERFECT-SILICON” 29 2.7 MINIMIZING PERFORMANCE-DEGRADATION CAUSED BY COPS THROUGH THE USE OF HIGH-PULL-SPEED SILICON 30 2.8 GETTERING FOR ULSI PROCESSES 32 2.8.1 Basic Gettering Principles 2.8.2 Extrinsic Gettering 2.8.3 Intrinsic Gettering 2.8.4 Gettering with Oxygen Precipitates 2.8.5 Summary of Gettering 2.9 STATUS OF SILICON WAFER TECHNOLOGY & FUTURE TRENDS 45 2.9.1 Epitaxy-Optimized Substrate (EOS) Wafers 2.9.2 Comparing the Grown-In Defect Characteristics of the “New” Wafers 2.9.3 Gettering Methods & Denuded Zone Formation Techniques Used with the “New” Wafers 2.9.3.1 “Magic DeNuded Zone”
2.10 FROM INGOT TO FINISHED WAFER: SLICING, ETCHING, & POLISHING 52 2.10.1 Ingot Evaluation 2.10.2 Ingot Surface Grinding 2.10.3 Grinding Flats or Notches on the Ingot for Orientation Purposes 2.10.4 Sawing the Ingot into Slices (Wafers) 2.10.5 Laser Marking the Wafers 2.10.6 Lapping and Grinding the Wafers 2.10.7 Removal of Surface Mechanical Damage by Chemical Etching 2.20.8 Rounding the Wafer Edge (and Notch) 2.10.9 Edge Polishing of the Wafers 2.10.10 Chemical-Mechanical Polishing of the Wafers 2.10.11 Cleaning the Wafers 2.10.12 Depositing Epitaxial Silicon Layers on the Wafers 2.10.13 Shipping 300-mm Wafers: Its Impact on the Evolution of Wafer Shipping Boxes 2.11 SPECIFICATIONS OF SILICON WAFERS FOR VLSI 63 2.12 THE ECONOMICS OF SILICON WAFERS 66 REFERENCES 69
Chap. 3 - GATE DIELECTRICS: THIN GATE OXIDES 3.1 REQUIRED CHARACTERISTICS OF GATE DIELECTRICS FOR DEEP-SUBMICRON MOSFETS 76 © 2002 LATTICE PRESS Sunset Beach CA All Rights Reserved
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CONTENTS 3.2 THE STRUCTURE OF THERMALLY GROWN SiO2 AND THE PROPERTIES OF THE Si/SiO2 INTERFACE 3.2.1 The Microscopic Structure of Thermally Grown SiO2 3.2.2 The Si/SiO2 Interface
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3.2.2.1 Interface Trap Charge 3.2.2.2 Effect of Interface Traps on IC Characteristics 3.2.2.3 Oxide Trapped Charge 3.2.2.3 Effect of Oxide Trapped Charge on Device Characteristics
3.3 DIELECTRIC BREAKDOWN IN SILICON DIOXIDE FILMS 90 3.3.1 Electron Trapping in Silicon Dioxide: 3.3.2 The Electric-Field Driven Model of Oxide Degr