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The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society. Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V.
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FULLY-DEPLETED SOI CMOS CIRCUITS AND TECHNOLOGY FOR ULTRALOW-POWER APPLICATIONS
Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications by
TAKAYASU SAKURAI University of Tokyo, Japan
AKIRA MATSUZAWA Tokyo Institute of Technology, Tokyo, Japan and
TAKAKUNI DOUSEKI NTT MicroSystem Integration Labs., Kanagawa, Japan
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN-10 ISBN-13 ISBN-10 ISBN-13
0-387-29217-9 (HB) 978-0-387-29217-5 (HB) 0-387-29218-7 (e-book) 978-0-387-29218-2 (e-book)
Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com
Printed on acid-free paper
All Rights Reserved © 2006 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed in the Netherlands.
CONTENTS
List of Contributors .............................................................................. xi Preface 1.
Introduction .........................................................................................1 1.1 1.2 1.3 1.4 1.5 1.6
2.
............................................................................... xiii
Why SOI? ..................................................................................1 What is SOI? — Structure — ..................................................2 Advantages of SOI ......................................................................4 History of the Development of SOI Technology.........................8 Partially-Depleted (PD) and Fully-Depleted (FD) SOI MOSFETs, and Future MOSFETs.............................................16 Summary ...................................................................................19 References .................................................................................20
FD-SOI Device and Process Technologies......................................23 2.1 2.2
Introduction ...............................................................................23 FD-SOI Devices ........................................................................24 2.2.1 Basic Features of SOI Devices ......................................24 2.2.2 Operating Modes of SOI MOSFETs .............................28 2.2.3 Basic Characteristics of FD- and PD-SOI MOSFETs ...32 v
2.3
2.4
2.5
3.
Ultralow-Power Circuit Design with FD-SOI Devices .................83 3.1 3.2 3.3 3.4
3.5
3.6
3.7
3.8
vi
Theoretical Basis of FD-SOI Device Operation: DC Operation ............................................................................48 2.3.1 Subthreshold Characteristics .........................................48 2.3.2 Post-threshold Characteristics .