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Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
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Low-Power High-Speed ADCs for Nanometer CMOS Integration
ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Titles in Series: LOW POWER UWB CMOS RADAR SENSORS Paulino, Nuno, Goes, João, Steiger Garção, Adolfo ISBN: 978-1-4020-8409-6 THE GM/ID DESIGN METHODOLOGY FOR CMOS ANALOG LOW POWER INTEGRATED CIRCUITS Jespers, Paul G.A. ISBN-10: 0-387-47100-6 SUBSTRATE NOISE COUPLING IN RFICS Helmy, Ahmed, Ismail, Mohammed ISBN: 978-1-4020-8165-1 CIRCUIT AND INTERCONNECT DESIGN FOR HIGH BIT-RATE APPLICATIONS Veenstra, Hugo, Long, John R. ISBN: 978-1-4020-6882-9 HIGH-RESOLUTION IF-TO-BASEBAND SIGMADELTA ADC FOR CAR RADIOS Silva, Paulo G.R., Huijsing, Johan H. ISBN: 978-1-4020-8163-7 MULTI-BAND RF FRONT-ENDS WITH ADAPTIVE IMAGE REJECTION A DECT/BLUETOOTH CASE STUDY Vidojkovic, V., van der Tang, J., Leeuwenburgh, A., van Roermund, A.H.M. ISBN: 978-1-4020-6533-0 SILICON-BASED RF FRONT-ENDS FOR ULTRA WIDEBAND RADIOS Safarian, Aminghasem, Heydari, Payam ISBN: 978-1-4020-6721-1 DESIGN OF HIGH VOLTAGE XDSL LINE DRIVERS IN STANDARD CMOS Serneels, Bert, Steyaert, Michiel ISBN: 978-1-4020-6789-1 BASEBAND ANALOG CIRCUITS FOR SOFTWARE DEFINED RADIO Giannini, Vito, Craninckx, Jan, Baschirotto, Andrea ISBN: 978-1-4020-6537-8 HIGH-LEVEL MODELING AND SYNTHESIS OF ANALOG INTEGRATED SYSTEMS Martens, Ewout S.J., Gielen, Georges ISBN: 978-1-4020-6801-0 CMOS MULTI-CHANNEL SINGLE-CHIP RECEIVERS FOR MULTI-GIGABIT OPT... Muller, P., Leblebici, Y. ISBN 978-1-4020-5911-7 ANALOG-BASEBAND ARCHITECTURES AND CIRCUITS FOR MULTISTANDARD AND LOW-VOLTAGE WIRELESS TRANSCEIVERS Mak, Pui In, U, Seng-Pan, Martins, Rui Paulo ISBN: 978-1-4020-6432-6 FULL-CHIP NANOMETER ROUTING TECHNIQUES Ho, Tsung-Yi, Chang, Yao-Wen, Chen, Sao-Jie ISBN: 978-1-4020-6194-3 ANALOG CIRCUIT DESIGN TECHNIQUES AT 0.5V Chatterjee, S., Kinget, P., Tsividis, Y., Pun, K.P. ISBN-10: 0-387-69953-8 SWITCHED-CAPACITOR TECHNIQUES FOR HIGH-ACCURACY FILTER AND ADC... Quinn, P.J., Roermund, A.H.M.v. ISBN 978-1-4020-6257-5 LOW-FREQUENCY NOISE IN ADVANCED MOS DEVICES von Haartman, M., Östling, M. ISBN 978-1-4020-5909-4 ULTRA LOW POWER CAPACITIVE SENSOR INTERFACES Bracke, W., Puers, R. (et al.) ISBN 978-1-4020-6231-5 BROADBAND OPTO-ELECTRICAL RECEIVERS IN STANDARD CMOS Hermans, C., Steyaert, M. ISBN 978-1-4020-6221-6 CMOS SINGLE CHIP FAST FREQUENCY HOPPING SYNTHESIZERS FOR WIRELESS MULTI-GIGAHERTZ APPLICATIONS