Advances In Electronic Testing: Challenges And Methodologies (frontiers In Electronic Testing)

ADVANCES IN ELECTRONIC TESTING CHALLENGES AND METHODOLOGIES FRONTIERS IN ELECTRONIC TESTING Consulting Editor Vishwani D. Agrawal Books in the series: Introduction to Advanced System-on-Chip Test Design and Optimi... Larsson, E., Vol. 29 ISBN: 1-4020-3207-2 Embedded Processor-Based Self-Test Gizopoulos, D. (Ed.), Vol. 28 ISBN: 1-4020-2785-0 Advances in Electronic Testing : Challenges and Methodologies Gizopoulos, D. (Ed.), Vol. 27 ISBN: 0-387-29408-2 Testing Static Random Access Memories Hamdioui, S., Vol. 26, ISBN: 1-4020-7752-1 Verification by Error Modeling Radecka, K. and Zilic, Vol. 25 ISBN: 1-4020-7652-5 Elements of STIL: Principles and Applications of IEEE Std. 1450 Maston, G., Taylor, T. (et al.), Vol. 24 ISBN: 1-4020-7637-1 Fault Injection Techniques and Tools for Embedded systems Reliability … Benso, A., Prinetto, P. (Eds.), Vol. 23 ISBN: 1-4020-7589-8 Power-Constrained Testing of VLSI Circuits Nicolici, N., Al-Hashimi, B.M., Vol. 22B ISBN: 1-4020-7235-X High Performance Memory Testing Adams, R. Dean, Vol. 22A ISBN: 1-4020-7255-4 SOC (System-on-a-Chip) Testing for Plug and Play Test Automation Chakrabarty, K. (Ed.) , Vol. 21 ISBN: 1-4020-7205-8 Test Resource Partitioning for System-on-a-Chip Chakrabarty, K., Iyengar & Chandra(et al.), Vol. 20 ISBN: 1-4020-7119-1 A Designers' Guide to Built-in Self-Test Stroud, C., Vol. 19 ISBN: 1-4020-7050-0 Boundary-Scan Interconnect Diagnosis de Sousa, J., Cheung, P.Y.K., Vol. 18 ISBN: 0-7923-7314-6 Essentials of Electronic Testing for Digital, Memory, and Mixed Signal VLSI Circuits Bushnell, M.L., Agrawal, V.D., Vol. 17 ISBN: 0-7923-7991-8 Analog and Mixed-Signal Boundary-Scan: A Guide to the IEEE 1149.4 Test … Osseiran, A. (Ed.), Vol. 16 ISBN: 0-7923-8686-8 ADVANCES IN ELECTRONIC TESTING CHALLENGES AND METHODOLOGIES Edited by DIMITRIS GIZOPOULOS University of Piraeus, Greece A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN-10 ISBN-13 ISBN-10 ISBN-13 0-387-29408-2 (HB) 978-0-387-29408-7 (HB) 0-387-29409-0 (e-book) 978-0-387-29409-4 (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springeronline.com Printed on acid-free paper All Rights Reserved © 2006 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed in the Netherlands. Contents Foreword xiii by Vishwani D. Agrawal Preface xv ii by Dimitris Gizopoulos Contributing Authors xx iii Dedication xx v Chapter 1—Defect-Oriented Testing 1 by Robert C. Aitken 1.1 History of Defect-Oriented Testing 2 1.2 Classic Defect Mechanisms 4 1.2.1 Shorts 4 1.2.2 Opens 6 1.2.3 Parametric Changes 7 1.3 Defect Mechanisms in Advanced Technologies 8 1.3.1 Copper-related Defects 8 1.3.2 Optical Defects 10 1.3.3 Design-related Defects 12 1.4 Defects and Faults 14 1.4.1 Uses of Fault Models 15 1.4.2 Single Stuck-at Faults 16 1.4.3 Bridging Faults 17 1.4.4 Open Fault Models 22 1.4.5 Timing-related or Delay Faults 24 1.4.6 IDDQ Models 27 vi Contents 1.5 Defect-Oriented Test Types 28 1.5.1 Logic Tests 28 1.5.2 Current-based Tests 29 1.5.3 Delay Test 31 1.5.4 Very Low Voltage 32 1.5.5 Stress Testing 33 1.6 Experimental Results 34 1.6.1 Fault Coverage, Scan vs. Functional 34 1.6.2 Effectiveness of IDDQ, Scan, At-speed Tests 34 1.6.3 Statistical Post Processing 39 1.7 Future Trends and Conclusions 39 Acknowledgments 40 References 40 Chapter 2—Failure Mechanisms and Testing in Nanom