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Biolding a Successful Board-Test Strategy This page intentionally left blank Building a Successful BoardTest Strategy Second Edition Stephen F. Scheiber BUTTERWORTH E I N E M A Boston Oxford N N Johannesburg Melbourne New Delhi Newnes is an imprint of Butterworth-Heinemann. Copyright © 2001 by Butterworth-Heinemann A member of the Reed Elsevier group All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher. Some material contained herein is derived from IEEE Std. 1014-1987, IEEE Standard for Versatile Backplane Bus: VMEbus, IEEE Std. 1049.1-1990, IEEE Standard Test Methods and Boundary-Scan Architecture, and IEEE Std. 1 1 55-1 992, IEEE Standard VMEbus Extensions for Instrumentation: VXIbus, copyrights by the Institute of Electrical and Electronics Engineers, Inc. The IEEE takes no responsibility for and will assume no liability for damages resulting from the reader's misinterpretation of said information resulting from the placement and context in this publication. Information is reproduced with the permission of the IEEE. Recognizing the importance of preserving what has been written, Butterworth-Heinemann © prints its books on acid-free paper whenever possible. Library of Congress Cataloging-in-Publication Data Scheiber, Stephen F. Building a successful board-test strategy / Stephen F. Scheiber. p. cm. Includes bibliographical references and index. ISBN 0-7506-7280-3 (pbk. : alk. paper) 1. Printed circuits-Testing. I. Title. TK7868.P7S34 2001 621.3815'310287-dc21 2001032680 British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library. The publisher offers special discounts on bulk orders of this book. For information, please contact: Manager of Special Sales Butterworth-Heinemann 225 Wildwood Avenue Woburn, MA 01 801-2041 Tel: 781-904-2500 Fax: 781-904-2620 For information on all Newnes publications available, contact our World Wide Web home page at: http://www.newnespress.com 10 9 8 7 6 5 4 3 2 1 Printed in the United States of America Contents Preface to the Second Edition x Chapter 1 What Is a Test Strategy? I 1.1 1.2 1.3 Why Are You Here? It Isn't Just Testing Anymore Strategies and Tactics 1.3.1 The First Step 1.3.2 Life Cycles 1.4 The Design and Test Process 1.4.1 Breaking Down the Walls 1.4.2 Making the Product 1.4.3 New Challenges 1.5 Concurrent Engineering Is Not Going Away 1.6 The Newspaper Model 1.6.1 Error Functions 1.6.2 What Do You Test? 1.6.3 Board Characteristics 1.6.4 The Fault Spectrum 1.6.5 Other Considerations 1.6.6 The How of Testing 1.7 Test-Strategy Costs 1.7.1 Cost Components 1.7.2 Committed vs. Out-of-Pocket Costs 1.8 Project Scope 1.9 Statistical Process Control 1.10 Summary 3 3 4 5 6 9 10 15 16 17 21 21 23 26 28 34 37 39 40 43 44 46 50 Chapter 2 Test Methods 53 2.1 The Order-of-Magnitude Rule 2.2 A Brief (Somewhat Apocryphal) History of Test 2.3 Test Options 2.3.1 Analog Measurements 53 55 58 59 vi BUILDING A SUCCESSFUL BOARD-TEST STRATEGY 2.3.2 Shorts-and-Opens Testers 2.3.3 Manufacturing-Defects Analyzers 2.3.4 In-Circuit Testers 2.3.5 Bed-of-Nails Fixtures 2.3.6 Bed-of-Nails Probe Considerations 2.3.7 Opens Testing 2.3.8 Other Access Issues 2.3.9 Functional Testers 2.3.10 Functional Tester Architectures 2.3.11 Finding Faults with Functional Testers 2.3.12 Two Techniques, One Box 2.3.13 Hot-Mockup 2.3.14 Architectural Models 2.3.15 Other Options 2.4 Summary 60 61 62 68 71 76 79 80 83 88 91 92 93 96 96 Chapter 3